Infotech Scheduled Drive for ASIC at Bangalore on 1st & 2nd Oct 2011
Job Description
We are conducting Scheduled Drive for HiTECH ASIC at Bangalore on 1st October & 2nd October 2011 (Saturday & Sunday).
Venue:
Hotel Grand Krishna, #77,
Hosur Main Road, Near Ayyappa Temple,
Madiwala, Bangalore-560068.
Contact Nos:080-25525723/4/ 09246372722.
Walkin Time: 10.00 AM to 3.00 PM.
Please refer your friends, relatives and acquaintances for these opportunities. Candidates should forward suitable profiles bef. 30th Sept (Friday), based on the suitability we can set up interviews with a date/time.
The Job Descriptions for these positions are mentioned below.
ASIC VERIFICATION (Job Code: ASIC-V)
Job Location : Hyderabad & Bangalore
Experience : 2 to 10 years’ experience in the following areas:
Job Location : Hyderabad ,Bangalore, Vizag & Noida.
Experience : 2 to 10 years’ experience in the following areas:
ASIC IMPLEMENTATION (Job Code: ASIC-IMP)
Experience : 2 to 10 years’ experience in the following areas:
Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification.
ASIC DFT (Job Code: ASIC-DFT)
Job Location : Hyderabad ,Bangalore & Vizag .
Experience : 2 to 10 years’ experience in the following areas:
Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools.
Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing.
Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision.
Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG.
Experience in Gate Level Simulations, Synthesis, STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug.
Programming in Perl, tcl, awk and c/c++.
Experience in DFT with Logic Vision tools is mandatory.
FPGA Engineers (Job Code: FPGA)
Job Location : Hyderabad
Experience : 2 to 10 years’ experience in the following areas
Ability to interface with silicon companies and understand their requirements and expectations.
Rapidly adapt to different design and verification environments
Coordinate efforts with offshore design and verification teams
Strong experience using System Verilog & OVM / VMM
Experience in Test Benches
ACTEL based experience would be an added advantage
Qualification for all the above positions: BE/B.Tech or ME/M.Tech/MS in respective streams.
Candidates who are unable to attend the drive can forward their resumes mentioning “Job Code & Years of Experience” in the Subject line to:
Please adv. Candidates to carry relevant documents for the
interview: Latest resume, academic qualification documents, Experience certificate, Latest 3 months payslips pay slips, etc.
Candidates who have attended interview with Infotech in the last 6 months are not eligible.
Best Regards,
Recruitment Team,
Infotech Enterprises Ltd.
Desired Profile
Experience 2 - 7 Years
Industry Type Semiconductors/ Electronics
Role Sr. Design Engineer
Functional Area Engineering Design, R&D
Education UG - B.Tech/B.E. - Any Specialization
PG - M.Tech - Any Specialization
Location Bengaluru/Bangalore, Delhi/NCR, Hyderabad / Secunderabad
Keywords ASIC, VLSI, FPGA, IMPLEMENTATION, SYSTEM VERILOG, systemverilog
Job Description
We are conducting Scheduled Drive for HiTECH ASIC at Bangalore on 1st October & 2nd October 2011 (Saturday & Sunday).
Venue:
Hotel Grand Krishna, #77,
Hosur Main Road, Near Ayyappa Temple,
Madiwala, Bangalore-560068.
Contact Nos:080-25525723/4/ 09246372722.
Walkin Time: 10.00 AM to 3.00 PM.
Please refer your friends, relatives and acquaintances for these opportunities. Candidates should forward suitable profiles bef. 30th Sept (Friday), based on the suitability we can set up interviews with a date/time.
The Job Descriptions for these positions are mentioned below.
ASIC VERIFICATION (Job Code: ASIC-V)
Job Location : Hyderabad & Bangalore
Experience : 2 to 10 years’ experience in the following areas:
Job Location : Hyderabad ,Bangalore, Vizag & Noida.
Experience : 2 to 10 years’ experience in the following areas:
ASIC IMPLEMENTATION (Job Code: ASIC-IMP)
Experience : 2 to 10 years’ experience in the following areas:
Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification.
ASIC DFT (Job Code: ASIC-DFT)
Job Location : Hyderabad ,Bangalore & Vizag .
Experience : 2 to 10 years’ experience in the following areas:
Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools.
Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing.
Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision.
Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG.
Experience in Gate Level Simulations, Synthesis, STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug.
Programming in Perl, tcl, awk and c/c++.
Experience in DFT with Logic Vision tools is mandatory.
FPGA Engineers (Job Code: FPGA)
Job Location : Hyderabad
Experience : 2 to 10 years’ experience in the following areas
Ability to interface with silicon companies and understand their requirements and expectations.
Rapidly adapt to different design and verification environments
Coordinate efforts with offshore design and verification teams
Strong experience using System Verilog & OVM / VMM
Experience in Test Benches
ACTEL based experience would be an added advantage
Qualification for all the above positions: BE/B.Tech or ME/M.Tech/MS in respective streams.
Candidates who are unable to attend the drive can forward their resumes mentioning “Job Code & Years of Experience” in the Subject line to:
Please adv. Candidates to carry relevant documents for the
interview: Latest resume, academic qualification documents, Experience certificate, Latest 3 months payslips pay slips, etc.
Candidates who have attended interview with Infotech in the last 6 months are not eligible.
Best Regards,
Recruitment Team,
Infotech Enterprises Ltd.
Desired Profile
Experience 2 - 7 Years
Industry Type Semiconductors/ Electronics
Role Sr. Design Engineer
Functional Area Engineering Design, R&D
Education UG - B.Tech/B.E. - Any Specialization
PG - M.Tech - Any Specialization
Location Bengaluru/Bangalore, Delhi/NCR, Hyderabad / Secunderabad
Keywords ASIC, VLSI, FPGA, IMPLEMENTATION, SYSTEM VERILOG, systemverilog